Research, industry & tools.

Graduate Research Assistant · PRISM Lab

University of Arizona · Advisor: Dr. Soheil Salehi

• Investigate large language models and agentic AI for hardware design and security, including RTL obfuscation for IP protection and post-synthesis validation of fault-hardening mechanisms.
• Contribute to power side-channel analysis and mitigation for FPGA and edge-AI systems, including correlation-based recovery from convolutional neural network outputs.
• Investigate standard-cell analysis methods for detecting and mitigating hardware Trojans in integrated circuits.
• Develop evidence-grounded, LLM-assisted security assessment methods across PCB design artifacts and the PCB assembly lifecycle.
• Designed a chip for photonic accelerator computing; final DRC and LVS verification are under way in preparation for tapeout.

• LLMs
• Agentic AI
• Side channels
• Hardware Trojans
• PCB security
• Photonics

Graduate Research Assistant · NECRL

San Francisco State University · Advisor: Dr. Hamid Mahmoodi

• Developed machine-learning-enabled interconnect modeling methods to improve the accuracy and efficiency of timing analysis for advanced semiconductor design.
• Ran simulation-based validation of interconnect models to assess timing-prediction accuracy.
• Developed automated analysis workflows for interconnect challenges caused by technology scaling.

• Machine learning
• STA
• Interconnect
• EDA

Energy Engineer · Industrial Assessment Center

San Francisco State University · Funded by the U.S. Department of Energy, Office of Energy Efficiency and Renewable Energy

• Co-led on-site energy assessments of industrial and manufacturing facilities to improve efficiency and reduce operating costs.
• Analyzed facility energy consumption, electrical loads and utility rate structures.
• Evaluated energy conservation measures through engineering calculations and economic analysis.
• Prepared technical assessment reports with findings, calculations and recommendations.

• U.S. DOE
• Energy efficiency
• Technical reporting

Teradyne J750 Automated Test Equipment

Training & volunteer service · NECRL Lab, San Francisco State University

The only student invited to volunteer during Summer 2025. Trained by a Teradyne professional in J750 calibration and operation, and used the system to test chips designed by students and alumni.

Verilog HDL: VLSI Hardware Design Comprehensive Masterclass

Udemy