Secure hardware, from transistors to systems.

Hardware Security & Trust

Modern chips are designed, fabricated and assembled by many parties across the globe, and every handoff is a chance for leakage, tampering or theft. I study how hardware can be attacked and how to detect and prevent those attacks.

• Power side-channel analysis and mitigation for FPGA and edge-AI systems, including correlation-based recovery of neural-network secrets.
• Standard-cell analysis methods for detecting and mitigating hardware Trojans in integrated circuits.
• Agentic LLM workflows for logic obfuscation that protect hardware intellectual property.

Papers

Secure Integrated Circuit Design

Security has to be built into the design flow, not added after tapeout. I work on methods that bring security checks into RTL design, synthesis and physical design.

• RTL obfuscation for intellectual-property protection, validated through functional and SAT-based security evaluation.
• Post-synthesis validation of fault-hardening mechanisms.
• Evidence-grounded security assessment across PCB design artifacts and the assembly lifecycle.

Papers

In-Memory Computing

Moving data between memory and compute now costs more energy than the computation itself. Compute-in-memory architectures address this, but they introduce new reliability and security questions. I explore secure, dependable in-memory computing for data-intensive and AI workloads.

• Security and reliability considerations of compute-in-memory fabrics.
• Hardware–software co-design for energy-efficient AI inference.

Status

Active Ph.D. research direction in the PRISM Lab

Trustworthy AI Hardware

AI now runs on edge devices, and large language models increasingly help write hardware. That raises two questions: can AI accelerators be trusted, and can the hardware that LLMs produce be trusted?

• Large language models and agentic AI for hardware design and security.
• Carbon-aware, privacy-preserving federated triage of weaknesses in LLM-generated Verilog.
• Side-channel resilience of on-chip learning and edge-AI accelerators.

Papers

Photonic Computing & Co-Packaged Optics for Space

Space systems need high bandwidth with very little power, mass and heat. Photonic computing and co-packaged optics can deliver that. I work on photonic accelerator hardware that can make it to silicon.

• Designed a photonic accelerator chip; final DRC and LVS verification are under way in preparation for tapeout.
• Co-packaged optics for high-bandwidth, power-efficient interconnects in space applications.

Project

Photonic accelerator chip · DRC/LVS verification before tapeout

Machine Learning for EDA

As transistors shrink, interconnect parasitics dominate delay and make timing analysis slower and less accurate. My M.S. thesis used machine learning to model interconnect for faster, more accurate timing analysis.

• ML-enabled interconnect modeling for timing analysis of advanced ICs (M.S. thesis).
• Simulation-based validation of timing-prediction accuracy.
• Automated analysis workflows for interconnect challenges caused by technology scaling.

Thesis

M.S. thesis · 3rd place overall, SFSU Project Showcase