Publications

Papers, preprints & chapters.

Peer-reviewed work on hardware security, LLMs for hardware design and trustworthy AI hardware at IEEE VTS, ACM GLSVLSI, ACM IGSC and PAINE. Live citation counts are on Google Scholar.

Highlights

Selected work

5Publications

2First-author

4Peer-reviewed venues

1Chapter in prep.

Featured · IEEE VTS 2026

Can Agents Secure Hardware? Evaluating Agentic LLM-Driven Obfuscation for IP Protection

An agentic, LLM-driven framework for automated netlist obfuscation that combines retrieval-grounded planning, structured lock synthesis, functional verification and SAT-based security evaluation.

Read on arXiv

Full list

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Conference proceedings

2026

PAINE 2026AcceptedFirst author

PCB-SAGE: LLM-Assisted Security Assessment with Grounded Evidence Across PCB Artifacts

P. Mirfasihi, S. Ghazali, X. Ramus, M. A. Chowdhury, S. Ghimire, P. Satam, and S. Salehi

in Proc. IEEE Physical Assurance and Inspection of Electronics (PAINE), 2026 — accepted for publication.

An evidence-grounded, LLM-assisted workflow that assesses security exposures across printed-circuit-board design artifacts and links every finding back to concrete assurance evidence across the PCB assembly lifecycle.

@inproceedings{mirfasihi2026pcbsage,
  title     = {PCB-SAGE: LLM-Assisted Security Assessment with Grounded Evidence Across PCB Artifacts},
  author    = {Mirfasihi, Parsa and Ghazali, S. and Ramus, X. and Chowdhury, Muhtasim Alam and Ghimire, Sujan and Satam, Pratik and Salehi, Soheil},
  booktitle = {Proceedings of the IEEE Physical Assurance and Inspection of Electronics (PAINE)},
  year      = {2026},
  note      = {Accepted for publication}
}

2026

ACM IGSC 2026PublishedFirst author

FedLLM4HW: Carbon-Aware Federated Triage of Hardware Weaknesses in LLM-Generated Verilog Code

P. Mirfasihi, A. Kim, H. Ramesh, J. Dean, M. Akbarsharifi, R. Akbarsharifi, et al.

in Proc. 16th ACM International Green and Sustainable Computing Conference (IGSC), 2026.

A privacy-preserving federated framework that ranks likely CWE-aligned weaknesses in LLM-generated RTL across organizations — without sharing proprietary designs — while scheduling participation by estimated carbon cost.

Publication page

@inproceedings{mirfasihi2026fedllm4hw,
  title     = {FedLLM4HW: Carbon-Aware Federated Triage of Hardware Weaknesses in LLM-Generated Verilog Code},
  author    = {Mirfasihi, Parsa and Kim, A. and Ramesh, H. and Dean, J. and Akbarsharifi, M. and Akbarsharifi, R. and others},
  booktitle = {Proceedings of the 16th ACM International Green and Sustainable Computing Conference (IGSC)},
  year      = {2026}
}

2026

IEEE VTS 2026Published

Can Agents Secure Hardware? Evaluating Agentic LLM-Driven Obfuscation for IP Protection

S. Ghimire, P. Mirfasihi, M. A. Chowdhury, V. Pugazhenthi, H. K. Dharavath, F. Firouzi, R. Yasaei, P. Satam, and S. Salehi

in Proc. 2026 IEEE 44th VLSI Test Symposium (VTS), pp. 1–5, 2026.

An agentic LLM framework for automated netlist obfuscation that combines retrieval-grounded planning, structured lock synthesis, functional verification and SAT-based security evaluation to protect hardware IP against an untrusted supply chain.

arXiv PDF

@inproceedings{ghimire2026agents,
  title     = {Can Agents Secure Hardware? Evaluating Agentic LLM-Driven Obfuscation for IP Protection},
  author    = {Ghimire, Sujan and Mirfasihi, Parsa and Chowdhury, Muhtasim Alam and Pugazhenthi, Veeramani and Dharavath, Harish Kumar and Firouzi, Farshad and Yasaei, Rozhin and Satam, Pratik and Salehi, Soheil},
  booktitle = {2026 IEEE 44th VLSI Test Symposium (VTS)},
  pages     = {1--5},
  year      = {2026}
}

2026

ACM GLSVLSI 2026Published

LeakSEAL: Power Side-Channel Leakage Analysis and Mitigation for Secure Edge AI Learning

V. Pugazhenthi, M. A. Chowdhury, S. Ghimire, H. K. Dharavath, P. Mirfasihi, et al.

in Proc. Great Lakes Symposium on VLSI (GLSVLSI), pp. 135–140, 2026.

Demonstrates correlation power analysis on a quantized spiking neural network running on an FPGA, recovering secret synaptic weights from as few as 1,500 power traces, and proposes mitigations for on-chip learning at the edge.

DOI

@inproceedings{pugazhenthi2026leakseal,
  title     = {LeakSEAL: Power Side-Channel Leakage Analysis and Mitigation for Secure Edge AI Learning},
  author    = {Pugazhenthi, Veeramani and Chowdhury, Muhtasim Alam and Ghimire, Sujan and Dharavath, Harish Kumar and Mirfasihi, Parsa and others},
  booktitle = {Proceedings of the Great Lakes Symposium on VLSI (GLSVLSI)},
  pages     = {135--140},
  year      = {2026},
  doi       = {10.1145/3787109.3816388}
}

Journal articles & preprints

2026

arXiv preprintSurvey

Large Language Models and Attention-Based AI for Hardware Design and Security: Progress, Challenges, and Opportunities

S. Ghimire, P. Mirfasihi, M. A. Chowdhury, H. K. Dharavath, B. Saber Latibari, M. Mamun, J. W. Carpenter, B. Tan, H. Pearce, F. Firouzi, K. Chakrabarty, R. Yasaei, P. Satam, and S. Salehi

arXiv preprint arXiv:2504.08854, 2026.

A survey of 30 representative approaches that use LLMs and attention-based models for RTL generation, verification, debugging and hardware security, with case studies and an agenda of open challenges.

arXiv PDF

@article{ghimire2026llmhw,
  title   = {Large Language Models and Attention-Based AI for Hardware Design and Security: Progress, Challenges, and Opportunities},
  author  = {Ghimire, Sujan and Mirfasihi, Parsa and Chowdhury, Muhtasim Alam and Dharavath, Harish Kumar and Saber Latibari, Banafsheh and Mamun, Muntasir and Carpenter, Jaeden Wolf and Tan, Benjamin and Pearce, Hammond and Firouzi, Farshad and Chakrabarty, Krishnendu and Yasaei, Rozhin and Satam, Pratik and Salehi, Soheil},
  journal = {arXiv preprint arXiv:2504.08854},
  year    = {2026}
}

Books & chapters

—

Book chapterIn preparation

Hardware Design Leveraging LLMs: From IP to SoC

Chapter 3 · Second author

in [Book title to be announced]. In preparation.